Electronic watch

ABSTRACT

A low cost electronic time keeping and display system comprising a regulated voltage converter for converting a low voltage from a source to a relatively high voltage, an electronic time keeping system powered by the low voltage source for providing low voltage time signals, and a plurality of level converters powered by the high voltage for converting each of the low voltage time signals to a relatively high voltage of sufficient magnitude to operate an associated relatively high voltage display. The regulated voltage converter periodically samples the relatively high voltage with a short duty cycle to minimize current consumption. Each level converter has a complementary configuration which consumes current only during an extremely short switching cycle. A single chip CMOS design, low voltage and current requirements and compatibility with liquid crystal display make the invention ideal for use in a watch environment.

United States Patent 1191 Strocka et al.

[ ELECTRONIC WATCH 75 Inventors: Richard L. Strocka; David F.

Broxterman, both of Sunnyvale,

Calif.

[73] Assignee: Cal-Tex Semiconductor, Santa Clara, Calif.

[22] Filed: 2, 1973 21 Appl. No.: 320,223

[52] US. Cl 58/50 R, 307/38, 340/336 [5 1] Int. Cl. G04b 3/12, G04c 3/00[58] Field of Search... 58/23 R, 23 A, 23 BA, 85.5;

Primary Examiner--Edith Simmons .lackmon Attorney, Agent, orFirm-Townsend and Townsend;

Warren P. Kujawa RESET 1111 3,815,354 1 June 11, 1974 [57] ABSTRACT Alow cost electronic time keeping and display system comprising aregulated voltage converter for converting a low voltage from a sourceto a relatively high voltage, an electronic time keeping system poweredby the low voltage source for providing low voltage time signals, and aplurality of level converters powered by the high voltage for convertingeach of the low voltage time signals to a relatively high voltage ofsufficient magnitude to operate an associated relatively high voltagedisplay. The regulated voltage converter periodically samples therelatively high voltage with a short duty cycle to minimize currentconsumption. Each level converter has a complementary configurationwhich consumes current only during an extremely short switching cycle. Asingle chip CMOS design, low voltage and current requirements andcompatibility with liquid crystal display make the invention ideal foruse in a watch environment.

19 Claims, 8 Drawing Figures RIQULATED VOLTAGE PATENTEDJUH H @1 3815354SHEET '4 BF 4 ELECTRONIC WATCH BACKGROUND OF THE INVENTION 1. Field ofthe Invention This invention relates to electronic time keeping devicesfor providing a correct indication of time. More particularly, thisinvention relates to systems employing electronic circuitry forgenerating correct time signals which can be fabricated in a singleintegrated circuit source .must of necessity have a correspondinglysmall dimensions. In addition, such a source must be economical toreplace. Although energy sources which I meet the required constraintson physical dimensions chip and housed in a typical watch case. In afurther aspect, this invention relates to circuitry for providing aregulated high level supply voltage from a relatively low voltage sourcefor supplying power to electronic time display circuitry. In a stillfurther aspect, this invention relates to level converter circuitry forconverting'time indicating signals from a relatively low voltage to arelatively high voltage for driving a time indicator display. v

2. Description of the Prior Art Time keeping devices are known whichemploy electronic circuitry for providing electrical signals serving toindicate the correct time. In a typical device, an extremely stable highfrequency oscillator supplies high frequency time base signals. Thesesignals are divided down by known circuitry which supplies a signaltrain .of pulses having a frequencyof 1 Hz. This signal train is coupledto a time keeping unit-comprising a number of counters which areincremented by the 1 Hz pulses. A scale of 60 counter provides a countrepresentative of the correct second of the minute. Another scale of 60counter provides a count representative of the cor rect minute of thehour. A scale of 12 counter provides a count representative of thecorrect hour of the day. In some devices, the hours counter is a scaleof 24 counter.

The outputs of the time keeping unit counters are decoded and typicallycoupled to a multi-digit seven segment or dot matrix display. As thecounters are clocked to different states by the 1 Hz clock pulses,various ones of the segments or dots are energized by the.decoded-counter outputs, thereby providing a visual output indicatingthetime.

Time keeping systems of the above type provide a degree of accuracywhich surpasses conventional mechanical movements, primarily due to thehigh frequency time base employed and the excellent frequency stabilityof electronic digital circuitry. Also, fully electronic systems are lessexpensive to manufacture than mechanical systems, and exhibit a muchlonger lifetime since there are no moving mechanical parts.

With the advent of large scale integrated circuits, attempts have beenmade to produce electronic time keeping systems for packaging in wrist,pocket, pendant and ring watch cases. Efforts at successful developmentof electronic watches have been impeded, however, by the problem ofpower consumption. Since all known electronic time keeping systems anddisplay devices consume electrical energy, an electronic watch must beprovided with a suitable portable energy source which is capable ofsupplying electrical energy at the requisite voltage and current levelfor a reasonably long period of time before replacement is required, theminimum desirable period being approximately 1 year. Because of therelatively small amount of volume available in a typical watch case,such a and cost are currently available, their voltage, current andpower ratings are extremely low.

' Given the desirability of using such available sources, however,recent developmental effortsin the field of electronic watches havefocused on designing electronic time keeping systems and associateddisplays which consume a minimal amount of current at the minimumvoltage required for error free operation of the device. Some effortshave concentrated on combining an electronic time keeping system with astandard mechanical watch display utilizing motor driven sweep typehour, minute and second hands. Other efforts have been directed to afully electronic system using an electronic time keeping system in'combination with an electrically actuated digital display utilizinglight emitting diodes. While the electronic time keeping portion of suchelectronic watches has been found to consume modest amounts ofelectrical'ene rgy, the power requirements of the display portion ofboth types have been found to be less than satisfactory for theabovenoted available energy sources.

Still other efi'orts to produce an electronic watch compatible withavailable low power, minimal size energy sources have been directedtoutilizing a liquid crystal display with an electronic time keepingsystem. While liquid crystal displays are available which meet theminimal size requirements for packaging purposes and which require onlymodest amounts of energy for proper operation, such displays require arelatively high voltage for proper actuation. Thus, known electronicwatches using a liquid crystal display have employed an electronic timekeeping system having two portions: one operated at a relatively lowvoltage, eg. 3 volts DC, for generating the 1 Hz reference pulses; theother operated at a relatively high voltage, eg. 15 volts DC, forproviding time indicating signals having a sufficiently great magnitudefor controlling the actuation of the liquid crystal display characters.This latter portion has heretofore employed a single discreet levelSUMMARY OF THE INVENTION The invention disclosed herein comprises a lowcost electronic time keeping and display system which operates from alow voltage energy source and consumes energy at a greatly decreasedrate than that of known systems. Because of the low operating voltageand low current consumption characteristics, systems constructedaccording to the-invention can be powered by commercially available, lowcost energy sources for prolonged periods in excess of one year withoutdeterioration of the time keeping accuracy thereof. In addition, sincevirtually all of the electrical components are housed in a singleintegrated circuit chip, the fabrication and assembly costs areextremely low.

as a liquid crystal display. The time keeping system includes acrystal-controlled high frequency oscillator, a divider circuit, a timekeeping unit, and a decoder section. The regulated voltage convertercomprises a constant current source, a voltage threshold detector, asense and enable circuit, and a sample circuit voltage converterincluding a ringing circuit. To minimize power consumption, theregulated voltage converter is arranged to periodically sample therelatively high voltage output, with each sample period having anextremely short duty cycle. Each level converter is arranged to drawcurrent only during an extremely short switching period. The preferredembodiment of theinvention is implemented with CMOS circuitry arrangedfor minimal power consumption.

For further understanding of the nature and advantages of theinvention,-reference should be had to the following description taken inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a system diagram of thepreferred embodiment of the invention;'

FIG. 2 illustrates a seven segment display character;

FIG. 3 is a block diagram of the time keeping unit of the preferredembodiment;

FIG. 4 is a diagram of a portion of the time keeping unit of FIG. 3;-

FIG. 5 is a block diagram of the regulated voltage converter of thepreferred embodiment;

FIG. 6 is a circuit diagram of the regulated voltage converter of FIG.5;

FIG. 7 is a circuit diagram of a pair of level converters, a transfergate and the shaper of the preferred embodiment; and FIG. 8 is a waveform diagram illustrating the operation of the preferred embodiment.

. DESCRIPTION OF THE PREFERRED EMBODIMENT Turning now to the drawings,FIG. 1 illustrates the preferred embodiment of the invention suitablefor use as an electronic watch. An oscillator 10 having a controlcrystal 12 provides a train of high frequency reference'pulsespreferably at a frequency of 32,768 Hz to the input of a frequencydivider circuit 14. Frequency divider circuit 14 divides the highfrequency reference signal down to 64 Hz, 32 Hz and 1 Hz referencesignals. The 64 Hz and 1 Hz reference signals are coupled to the inputof a time keeping unit 16, shown in detail in FIGS. 3 and 4, whichprovides output signals representative of minutes and hours to a decoderunit 18.

Decoder unit 18 is provided with a plurality of output leads 19 -19,-each coupled to a low voltage control input terminal of a differentlevel converter 20 -20,. It is noted that the 1 Hz output signal fromdivider 14 is also coupled directly to a level converter 20,.

The output of each level converter 20 -20,- is coupled to the controlinput of a different transfer gate 20 -20,. The output of each transfergate 22 -22,- is a high level signal for enabling a different one of aplurality of display segment control electrodes 24 -24,- of a liquidcrystal display 25.

In the preferred embodiment, liquidcrystal display 25 is arranged as aplurality of -7 segment digital display characters, each similar to theseven segment character illustrated in FIG. 2. Each character comprisesseven individual segments a-g, each of which is actuatable in responseto the application thereto of an enabling or striking potential. Byselectively actuating different combinations of the individual segmentsa-g, the decimal digits 09 may be displayed. In the preferred embodimenttwo such characters are used for indicating minutes and two charactersfor indicating hours. A special segment 24 is pulsed at a I second rateby the I Hz signal on lead 19 to provide a visual indication to thewearer that the electronic watch is functioning properly. The structureand operation of liquid crystal displays are well known and furtherstructural details of display 25 are accordingly omitted to avoidprolixity. Such displays are characterized by relatively low currentconsumption compared to light emitting diode displays or other knowntypes of displays suitable for use as time indicators. However, forproper operation a liquid crystal display requires the application of arelatively high enabling potential between a given segment 24 and thecommon electrode 30. Moreover, this relatively high enabling potentialis preferably applied in an A.C. mode as described below in order toprolong the life of the display.

As will be apparent, the number of level converters 20 40,, transfergates 22 -22, and display segment control electrodes 24 -24,- isdetermined by the number of desired reference characters and the numberof segments per characterrTo avoid needless repetition, the majority ofsuch elements have been indicated in the FIG. 1 diagram by broken lines.

A low voltage source 26 providing a source voltage V of approximately1.5 volts DC in the preferred embodiment is coupled to the supplyvoltage input of oscillator l0, divider unit 14, time keeping unit 16and decoder. unit 18. Low voltage source 26 is also coupled to aregulated voltage converter 27 which converts the relatively low voltagefrom source 26 to a relatively high voltage of the order ofapproximately 15 volts DC in the preferred embodiment. The output fromregulated voltage converter 27 is coupled to the supply voltage input oflevel converters 20 -20,, a level converter 20, and a shaper 29. Thehigh leveloutput of the shaper 29 is coupled to the transfer inputs oftransfer gates 22 -22, and to common electrode 30 of liquid crystaldisplay 25.

As will now be apparent, oscillator 10, divider 14, time keeping unit 16and decoder 18 are all powered by the relatively low voltage V fromsource 26. Since these units are all well known to those skilled in theart their details have been omitted to avoid prolixity. These units arepreferably implemented by CMOS circuitry. As will be evident to thoseskilled in the art, cirsuch circuits require extremely small amounts ofcurrent for proper operation. In addition, such circuits can readily bedesigned to function properly from 'extremely low supply voltage. Thus,low voltage source 26 may comprise any one of a number of commerciallyavailable 1.5 volt DC batteries.

In operation, the train of high frequency reference pulses fromoscillator) is divided down by divider 14 to the 64 Hz, 32 Hz and 1 Hztime reference signals. The 1 Hz reference signals are applied totimekeeping unit 16 which provides a minutes and hours count in responsethereto. The minutes and hours signals from time keeping unit 16 aredecoded by decoder unit 18 into low level signals on leads 19 -19 forspecifying the individual segments 24,-24, of liquid crystal displaywhich are to be actuated in order to provide a visual time indication.The low level 1 Hz reference signals on lead 19 are also utilized tospecify the actuation of seconds segment 24 of liquid crystal display25.

' Level converters 20 -20,- and 20,-, transfer gates 22 -22,- and shaper29 are all operated at a relatively high potential V provided byregulated voltage converter 27. Level converters 20 40, convert the lowlevel control signals at their respective inputs 119 -49,- to high levelcontrol signals for operating transfer gates 22 -22,-. Level converter20,- converts the low level 32 Hz control signal present on input lead19,-to high level 32 Hz signals. These high level signals from levelconverter 20,- are shaped by shaper 29 to provide high level 32 Hzsegment actuation signals with sharply defined leading and trailingedges. The segment actuation signals are'coupled through transfer gates22 -22, to segments 24 -24, and directly to common electrode of liquidcrystal display 25. As more fully described below in connection withFIGS. 7 and 8, transfer gates 22 22, control the phase of the segmentactuation signals coupled therethrough with reference to the phase ofthe segment actuation signal coupled directly to common electrode 30.When the segment actuation signals on a given segment 24,- and commonelectrode 30 are in phase, that segment is not displayed; when segmentactuation signals are out of phase that segment is actuated. Thus,various segments of the minutes and hours digit characters are displayedor not depending on the low level output signals on leads 19 -19. fromdecoderunit 18. In this manner, the various digits indicating minutesand hours are displayed.

An important feature of the invention shown in FIG. 1 resides in theoperation of the time keeping system comprising oscillator 10, dividerunit 14, time keeping unit 16 and decoder unit 18 at the low voltagelevel V provided by source 26 and the operation of the level converters20 -20,, 20 transfer gates 22 -22, and shaper 29 at the high voltagelevelV provided by regulatedvoltage converter 27. Because of the lowvoltage operation of the time keeping system and the use ofcomplementary semiconductor circuitry, the power consumption of thecontinuously operating time keeping system is held to a minimum. Becauseof the complementary semiconductor circuit configuration of the highlevel operated level converters 20 -20,, 20;, gates 22 -22,- and shaper29, power consumption of this relatively high voltage portion of thepreferred embodiment is also held to a minimum.

Time keeping unit l6, as shown in FIG. 3 comprises a divide-byunit 31, aminutes counter 32, an hours counter 33 and a time adjust unit 34. Thedivide-by-6O unit 31 produces an output pulse at 60 second intervalsfrom the 1 Hz input signal. Each output pulse from unit 3]. incrementsminutes counter 32 which may comprise a scale of 60 counter or a scaleof 10 counter followed by a scale of 6 counter. The last stage ofminutes counter 32 produces an output pulse at 1 hour intervals. Eachsuch output pulse increments hours counter 33, which may comprise ascale of 12 counter or a scale of 24 counter, the latter being utilizedwhen a 24 hour time system is desired. Such counters are well known inthe art and accordingly are not described in detail.

Time adjust unit 34 is arranged to gate 64 Hz signals to divide-by-60unit 31 along with a DISABLE signal for preventing the 1 Hz input signalfrom operating unit 31, and 1 Hz signals to minutes counter 32 or hourscounter 33, all in response to'time adjust signals from an operatorcontrol device. The operator control device comprises any operatoradjustable device for providing minute and hour advance signals. Onesuch arrangement comprises a pair of switches: one signifying minutesadjust; the other hours adjust; each operable by a different buttonprotruding from the watch case. Other equivalent arrangements will occurto those skilled in the art. The 64 Hz input to divide-by-60 unit 31clocks this unit to a predetermined initial state whenever minutescounter 32 is being adjusted. Once unit 31 reaches this initial state,application of the 64 'Hz signal to unit 31 is terminated. Thereafter,the DIS- MINUTES ADJUST signal inverted by an Inverter 38 disables anAND gate 39 from transmitting 1 Hz pulses to OR gate 37. When the laststage of divide-by60 unit 31 is set, a reset signal is applied to thereset input of flip-flop 35. When flip-flop 35 resets, AND gate 36 isdisabled. AND gate 39 continues disabled until the MINUTES ADJUST signalis removed.

The minutes time adjust is effected by applying 1 Hz pulses to minutescounter 32 until the proper count has been attained. During this timethe minutes section of liquid crystal display 25 provides a visualindication of the setting in minutes counter 32. The hours adjust isaccomplished in a similar manner.

The various stages of minutes counter 32 and hours counter 33 arecoupled to decoder unit 18. Decoder unit 18 comprises known logiccircuitry for decoding various counter settings into control signals forspecifying the proper character segments for actuation in accordancewith the counter settings to form the corre sponding digit characters.Since circuitry for performing this function is well known to thoseskilled in the art, further details thereof have been omitted to avoidprolixity.

An important feature of the invention comprises the regulated voltageconverter 27 shown in block diagram form in FIG. 5. A constant currentsource 41 supplies a small constant current to a voltage droppingresistor 42. In the preferred embodiment the approximate value of thiscurrent is l microamp. The opposite end of resistor 42 is coupled to therelatively high voltage output V of a voltage converter 44. Since thecurrent through resistor 42 is substantially constant, the voltage dropthereacross is also constant. ThuS, any variation in the magnitude of Vresults in a linear variation of the voltage V, at junction 45, Le. V,V=K a constant. The voltage V, at junction 45 is sensed by a thresholddetector 46 which provides an output signal whenever the magnitude ofvoltage V, falls below a first predetermined value, indicating that themagnitude of voltage V,, has fallen below a second predetermined valuelinearly related to the first predetermined value by the constant K. Asense and enable circuit 47 enables voltage converter 44 whenever theoutput of threshold detector 46 indicates that the magnitude of voltageV has fallen below the predetermined value. When enabled, voltageconverter 44 converts the relatively low voltage V from low voltagesource 26 to a relatively high voltage V A samplecircuit 48 controlsconstant current source 41, threshold detector 46 and sense and enablecircuit 47 to provide periodic, interrupted operation of these elements.In the preferred embodiment, a sampling rate of 4 Hz is employed, theactual sample period being I millisecond. Other sampling rates andperiods may be employed as desired. As noted above, in the preferredembodiment the relative magnitudes of V and V,, are approximately 1.5volts DC and 15 volts DC respectively.

4 Voltage converter 44 also converts relatively low voltage V to' abiasing voltage V having a magnitude of approximately 1.5 volts DC belowthe magnitude of V,,'. In the preferred embodiment bias voltage V isderived from voltage V,, and thus is not separately sampled andreplenished. If desired, however, separate sensing and replenishingcircuitry may be employed for voltage V As discussed more fully below,voltage V provides a bias voltage for the operation of level coniverters 20 -20,, 20,.

' the elements comprising the various blocks shown in FIG. are enclosedin broken rectangles bearing the same reference numeral.

Voltage converter 44 may be considered as comprising a first portiondepicted at the right of the Fig. for generating voltage V,,' and asecond portion depicted at the. left of the Fig. for generating voltageV The first portion comprises a pair of complementary MOS transistors50, 51 connected in a push-pull buffer configuration for providing ahigh driving current to a discreet transistor 52. Transistor 52 togetherwith an inductance 53, a rectifying diode 54 and a capacitor 55 comprisea voltage ringing circuit for converting the relatively low'voltage V atterminal 56 to a relatively high voltage V,, at terminal 57. Transistor50 is normally biased on and transistor 51 is normally biased off by thequiescent low level input signal to their commonly connected gates. Aground potential is thus applied through transistor 50 to the base ofdiscreet transistor 52, maintaining this element non-conductive. Whenthe level of the signal coupled to the gates of transistors 50,51changes, the states of these two elements reverse. Thus, relatively lowpotential V from terminal 56 is applied through transistor 51 to thebase of the remaining data input of discreet transistor 52 turning thiselement on, thereby permitting current to flow through inductor 53. Whenthe level of the gate input signal to transistors 50, 51 reverts to thequiescent level, these elements again reverse states. turning offdiscreet transistor 52. The change of current through inductor 53 causesthe development of a high voltage thereacross, which is rectified bydiode 54 and stored by capacitor 55. After several initial cycles, thevoltage at terminal 57 builds up to the desired magnitude V,,. In thismanner, this first portion of voltage converter 44 converts therelatively low supply voltage V,, from low ,voltage source 26 to therelatively high voltage-V present on terminal 5.7.

The second portion of voltage converter 44 comprises a p-type MOStransistor 60 which is permanently biased on by voltage V,,'to supplycurrent to a pair of N-type MOS transistors 61,62 configured as shown.The source terminal of lower transistor 62 is coupled to voltage V,,'.Transistors 61,62 provide a constant voltage drop to voltage V toestablish bias voltage at terminal 63.

Constant current source 41 includes an N-type MOS transistor 65 and apair of P-type MOS transistors 66,67 configured as shown as the mirrorimage of transistors 60,61, 62 to provide a constant voltage to the gateof a P-type MOS transistor 68. Transistor 68 provides a constant currentto a first terminal of resistor 42 whenever a first P-type MOS switchingtransistor 70 is turned on in the manner described below. As notedabove, the opposite terminal'of resistor 42 is coupled to voltage VSense and Enable circuit 47 includes a pair of P-type MOS transistors72,72 which are permanently biased on by voltage V applied to theirrespective gates whenever a second P-type MOS switching transistor 71 isswitched on in the manner described below. Transistor 72 serves as aload for a P-type MOS transistor connected as a source follower, whiletransistor 73 serves as a load for an N-type MOS sensing transistor 76.Transistor 75 provides a voltage drop to voltage V, at junction 45 sothat the voltage variations on the gate of sensing transistor 76 fallwithin an operative range. In addition, the voltage drop provided bysource follower transistor 75 ensures that the voltage on junction 45remains within a range that maintains the operation of transistor 68 inthe constant current mode. So long as the magnitude of voltage V is notbelow the predetermined threshold value, sensing transistor 76 is biasedoff by the voltage present at the gate thereof. However, when themagnitude'of voltage V drops below this threshold value, sensingtransistor 76 is biased on and the normally high signal at the outputthereof drops to a low level.

The output from sensing transistor 76 is coupled directly to a firstdata input of a flip-flop 77 and through an inverter 78 to the remainingdata input thereof. The

clock input signal to flip-flop 77 is a train of 4 Hz pulses eachapproximately 1 millisecond in duration obtained from sample circuit 48,described more fully below. Flip-flop 77 provides a control input signalto an inverting OR gate 80 which provides enabling control signals tothe first portion of voltage converter 44.

The other input to inverting OR gate 80 is obtained from the output ofan inverting AND gate 82. The inputs to inverting AND gate 82 are a 256Hz and a 32K l-Iz pulse train, obtained from appropriate stages ofdivider circuit 14 of FIG. 1, and the O output of a flipflop 83, whichis a J-K flip-flop in the preferred embodiment. The 256 Hz pulse trainis applied directly to a first data input of flip-flop 83 and through aninverter 84 to thereof. As will be apparent to those skilled in the art,inverter 84, flipflop 83 and inverting AND gate 82 comprise a leadingedge detector which develops negative-going pulse signals ofapproximately 15 microseconds duration each at a rate of 256 Hz from the256 Hz and the 32K [-12 pulse trains. Thus, when flip-flop 77 is in thereset state, inverting OR gate 80 transmits these pulse signals to thecommonly-connected gates of transistors 50,51 of voltage converter 44.Conversely, when flip-flop 77 is set, inverting OR gate 80 blocks thetransmission of these pulse signals to voltage converter 44.

Sample circuit 48 comprises a sample pulse generator, an inverter 86 andthe aforementioned first and second switching transistors 70,71. Thesample pulse generator comprises a flip-flop 87, which is a .l-Kflipflop in the preferred embodiment, an inverter 88 and an inverting ORgate 89. A 4 Hz pulse train is coupled directly to a first data input offlip-flop 87 and through inverter 88 to the remaining data input offlip-flop 87.

A 1,024 Hz pulse train is applied to the clock input of flipflop 87.Both pulse trains are obtained from appropriate stages of dividercircuit 14 of FIG. 1. The Q output of flip-flop 87 is coupled to theinput of inverting OR gate 89 along with the inverted 4 Hz pulse train.As will be apparent to those skilled in the art, inverter 88, flip-flop87 and inverting OR gate 89 comprise a leading edge detector whichdevelops positive-going pulse signals of approximately 1 millisecondduration each at a rate of 4 Hz from the 4 Hz and 1,024 Hz pulse trains.As noted above, these'pulse signals are applied directly to the clockinput of flip-flop 77. Thus, the input to flipflop 77 is sampled 4 timesper second. These pulse signals are also inverted by inverter 86 andapplied to the gates of switching transistors 70,71. Since switchingtransistors 70,71 enable constant current source 41 and thresholddetector 46, respectively, these circuits are each enabled concurrentlyfor l millisecond at the rate of 4 times per second in synchronism withthe sampling of flip-flop 77.

In operation, when power from voltage source 26 of FIG. 1 is firstapplied to the various V terminals of regulated voltage converter 27,the voltage at terminal 57 lies below the predetermined threshold value.Sensing transistor 76 is biased on and flip-flop 77 is reset by thefirst clock pulse, thereby enabling inverting OR gate is set by thesucceeding clock pulse, blocking inverting OR gate 80. Thereafter,inverting OR gate 80 remains blocked until the magnitude of voltage Vdrops below the predetermined threshold value, causing sensingtransistor 76 to be biased on, which in turn enables flip- 10 flop 77 tobe reset by a succeeding clock pulse. During this operation, themagnitude of the voltage V,, at terminal 63 follows the variations inthe magnitude of the voltage on terminal 57.

As will now be apparent to those skilled in the art, regulated voltageconverter 27 provides an extremely well regulated high voltage V and arelated bias voltage V required for the operation of level converters 20-20,, 20, and liquid crystal display 25. The intermittant operation ofconstant current source 41 and threshold detector 46, the small dutycycle provided by sample circuit 48 and the complementary transistordrive configuration of voltage converter 44 all serve to reduce thepower consumption of regulated voltage converter 27 well below thatrequired for prior art voltage converter circuits providing conversionof a relatively low voltage to a relatively high voltage. The powerconsumption of regulatedvoltage converter 27 is further reduced by theuse of CMOS circuitry for implementing flip-flops 77,83 and 87, and theuse of MOS devices for the elements as shown and for the inverters andgates symbolically illustrated.

FIG. 7 illustrates the actual circuitry employed in the preferredembodiment for implementing level converter 20,, shaper 29 and levelconverter 20,- and transfer gate 22}, the latter circuitry being typicalof level converters 20 40,- and transfer gates 22 -22,. In this Fig. theelements comprising the various blocks shown in FIG. 1 are enclosedinbroken rectangles bearing the same reference numeral.

Level converter 20,- includes a first and second pair of P-type MOStransistors 100, 101 and 102, 103, respectively, each pair beingconnected source-to-source and drain-to-drain as shown. Thecommonly-connected sources of each pair are coupled to ground potential.The gate of each inner transistor of each pair is coupled to the commondrain terminal of the other pair. The

gate inputs to outertransistors 100,103 are the 32 Hz reference signalson lead 19, from'divider 14 of FIG. 1 and the output of an inverter 105,respectively. The common drain terminal of each pair is coupled to thedrain terminal of a different N-type MOS transistor 106,107respectively. The gate of each transistor 106,107 is coupled to the gateof the associated inner transistor 101,102 respectively. A constantcurrent source comprising an N-type MOS transistor 108 having relativelyhigh voltage V coupled to the source terminal thereof and biasingvoltage V coupled to the gate thereof in order to permanently biastransistor 108 on is provided in the left main branch of level converter20 An identically configured constant current source comprising N-typeMOS transistor 109 is provided in the right branch of level converter20;.

In operation, with enabling voltages V and V applied to transistors108,109 and the low level input signal on terminal 19, at the truelevel, transistor .100 is biased off. The inverted input signal frominverter 105 is false and transistor 103 is thus biased on. U; is thusat ground potential and biases transistor 101 off and transistor 106 on.Since transistor 106 is biased on by Q, and transistor 108 is biased onby voltage V,,, O,

amp whenswitching.

on and transistor 107 off.

When the low level input signal on terminal 19, transitions false,transistor 100 is biased on and transistor 103 is biased off. Sincetransistor 100 is now on, the voltage at Q, rises to ground potential,turning transistor 102 off and transistor 107 on. As transistor 102 isbiased off, the voltage at Q, falls to V,,', biasing transistor 101 onand transistor 106 off. The circuit remains latched in this state untilthe inputv signal on lead 19,- transitions true. I

When the low level input signal on lead 19," transitions true,transistor 100 is biased off and transis tor 103 is biased on. Astransistor 103 is biased on, the voltage at Q,- rises to groundpotential, biasing transistor101 off and transistor 106 on. Astransistor 106 is biased on, the voltage at Q, falls to V biasingtransistor 102 on and transistor 107 off. The circuit remains latched inthis state until the input signal on lead 19, again transitions false.Further operation of level converter 20, proceeds as already described.

As will now be apparent, level converter 20, provides a pair ofoppositely phased output signals on terminals Q,, O, which range inmagnitude between a negative voltage V having a relatively highmagnitude and ground potential in response to an input signal on lead 19,which ranges in magnitude between a negative voltage V having arlatively low magnitude and ground potential. As noted above, in thepreferred embodiment the range on the magnitude of the input signal isapproximately l.5 volts DC while the range on the magnitude of theoutput signal is approximately O-l5.0 volts DC. Thus, level converter 20as well as level converters 20,20,-, permit the low voltage portion ofthe electronic time keeping system to control the relativelyhigh voltagedisplay. It is important to note that level converter 20, draws currentonly during the extremely short transitional periods when the circuit isbeing switched between opposite latched states, due to the complementaryconfiguration of the circuit. Thus, the current consumption of levelconverter 20, is extremely small and discontinuous, being of the orderof 1 micro- The ogtput signals from level converter 20, on leads Q, andQ, are coupled to the control gate of complementary MOS transistors 110,111, 112, 113, respecis coupled directly to common electrode of liquidcrystal display 25. The output signals on Q and 629 ased on and thesignal on Q29 is transmitted to'display seg n ient 24,-. Conversely,whenever the output signal on Q, is high and the output signal of Q, islow, tra nsistors 122 and 123 are biased on and the signal of 0 istransmitted to display segment 24,.

Level converter 20, is substantially identical in configuration toabove-described level converter 20,. The input signal to level converter20,, however, is a relatively low frequency time control signal fromdecoder unit 18, it being remembered that the control signals change atthe maximum rate of l per minute for segments representing the 'unitsminutes'characters and the minimum rate of l per 12 hours for segmentsrepresenting the tens hours character. Due to the relatively lowfrequency of the control signals applied to-level converter 20,-, it isnot necessary to shape the output signals from this element present onterminals Q5, Q1.

The output signals from level converter 20, control the phase of thecommutated square wave signal applied to display segment 24, relative tothe phase of the commutated square wave signal applied to common arecoupled to transmission gates 22 -22,, only one of I which is shown inFIG. 7.

Transmission gate 22,- comprises two pair of parallel connected CMOStransistors 120, 121 and 122, 123 respectively. The gates of CMQStransistors 121,122 are commonly connected to theQi Output terminal oflevel converter 20,. Similarly, the gates of CMOS transistors 120,123are commonly connected to the 0, output terminal of level converter 20,.Whenever the output signal on Q, is high (ground potential) and theoutput signal on Q, is low (V,,') transistors and 121 are bielectrode30. This is best illustrated with reference to FIG. 8. Wave form Arepresents the relatively low level 32 Hz square wave input signal tolevel converter 20,

present on lead 19,-. Wave forms B and C illustrate the- 32 Hzrelatively high level output signals from shaper 29 present on outputterminals Q Q respectively.

Wave form D illustrates the relatively low level control terminals Q,and Q, respectively. Wave form G illustrates the output signal fromtransfer gate 22, coupled to display segment 24,. Wave form Hillustrates the signal from terminal Q coupled to common electrode 30 ofliquid crystal display 25. For economy of space all of the above waveforms are represented in abbreviated form indicated by thebroken'centralportion.

When wave forms G and H are in phase, the potential difference betweendisplay segment 24, and common electrode 30 is zero and the segment 24,is off. Conversely, when wave lforms G and H are out of phase a strikingpotential is established between segment 24, and common electrode 30 andsegment 24, is on. The relative phase of wave forms G and H isdetermined by control waveform D. When this control signal is true, waveforms E and F are false and true respectively, and wave form G followswave form H. When wave form D is false wave forms E and Fare true andfalse, respectively, andwave form G is oppositely phased from wave formH. Thus, with segment 24, initially off, indicated by the hatched area,when wave form D transitions false segment 24, is turned on as indicatedby the unhatched area. When wave form D again transitions true, segment24, is again turned off. 1

In the preferred embodiment, each segment 24, is operated in an AC. modeby reversing the direction of the potential between the segment andcommon electrode 30 at the arbitrary rate of 32 Hz. This mode ofoperation of all character segments is utilized in order to prolong thelife of liquid crystal display 25. When the preferred embodiment is usedto drive other types of relatively high voltage display devices, A.C.operation 20 -20, and level converter 20,, transmission gates 22 22,-,and shaper 29 may be omitted.

The entire electronic time keeping and display system disclosed hereincan be virtually fabricated from a single integrated circuit chip, theoutline of which is outlined in FIG. 1, by the phantom-lined borderindicated by reference character C. As indicated by this Fig, the onlycomponents which are not included in the single integrated circuit chipare oscillator crystal 12, low voltage source 26, which must beremovable when exhausted, and a portion of regulated voltage converter27. With reference to FIG. 6, those elements ofregulated voltageconverter 26 which are not housed in the single integrated circuit chip,also outlined in phantom in this Fig, are resistor 42 and the discreetelements of voltage converter 44: viz, transistor 52, inductor 53,

diode 54 and capacitor 55. Thus, only seven circuit elements one ofwhich must be readily replacable are carried externally of the singleintegrated circuit chip. As will be evident to those skilled in the art,this enables the electronic time keeping system of the invention to befabricated and assembled at an extremely low cost. I

Referring again to FIG. 1, liquid crystal display 25 comprises aseparate physical package, indicated by the phantom-lined border D, fromthe integrated circuit chip, and may be arranged relative thereto in anyconvenient manner. In one suitable packaging arrangement employed in thepreferred embodiment, the liquid crystal display package D is mountedabove the integrated circuit chip, and this assembly is placed in awatch case with the liquid crystal display characters visible throughthe watch case crystal. Other equally suitable mounting arrangementswill occur to those skilled in the art.

As will now be evident to those skilled in the art, the electronic timekeeping and display system disclosed herein provides a highly accurate,readily visible time display and is sufficiently small to be easilyaccommodated by the various types of watch cases known in the art.Further, the disclosed system is powered by a single, readily availablelow cost battery which is easily replacable when exhausted. Moreover,due to the low voltage and current requirements, the latter amounting toan average drain for the entire circuitry of only approximatelymicroamperes, and the resulting low power consumption of the electroniccircuitry, electronic watches constructed according to the invention canoperate on the same low voltage source in excess of one year beforereplacement of the source becomes necessary.

As will be further evident to those skilled in the art, the levelconverters utilized in the electronic time keeping system enable the lowvoltage time control signals to control the operation of the highvoltage display without consuminggreat quantities of current, therebycontributing to the efficient low power operation of the entire system.In addition, the regulated voltage converter utilized in the electronictime keeping system provides a well-regulated source of relatively highvoltage for operating the level converters and the display also withoutconsuming substantial amounts of current, which further contributes tothe efficient low power operation of this system.

While the above provides a full and complete disclosure of the preferredembodiment of the invention, various modifications, alternateconstructions and equivalents may be employed without departing from thetrue spirit and scope of the invention. Therefore, the above descriptionand illustrations should not be construed as limiting the scope of theinvention which is solely defined by the appended claims.

What is claimed is:

L'An electronic timekeeping system characterized by low powerconsumption, said system comprising a source of relatively low DC.voltage;

means for converting the output from said source of relatively lowvoltage to a relatively high D.C. voltage;

a source of relatively low voltage clock pulses;

a time signal generator coupled to said source of clock pulsesforproviding a plurality of time signals having a magnitude of the orderof said low voltage, said clock pulse source and said time-signalgenerator being-coupled to and powered by said source of relatively lowDC. voltage; and

level converting means coupled to said time signal generator and saidvoltage converting means for converting individual ones of saidplurality of low voltage time signals to display actuation signalshaving a magnitude of the order of said relatively high DC. voltage. i

2. The apparatus of claim 1 further including display means coupled tosaid level converter means and operable by said relatively'high voltagedisplay actuation signals for generating visible time indicia inresponse to said time signals. I v

3. The apparatus of claim 2 wherein said display means comprising aliquid crystal display having a plurality of seven-segment digitcharacters.

4. The apparatus of claim 1 wherein said voltage converting meansincludes means for maintaining the magnitude of said relatively highvoltage above a predetermined threshold value.

5. The apparatus of claim 4, wherein said maintaining means includes athreshold detector for generating an enabling signal when the magnitudeof said high voltage decreases to said predetermined threshold value.

6. The apparatus of claim 5, wherein said maintaining means furtherincludes sample means for periodically sampling the output of saidthreshold detector, and sense and enable means for generating a controlsignal adapted to actuate said voltage converting means in response tothe generation of said enabling signal.

7. The apparatus of claim 6, wherein said sample means includes meansfor limiting the duration of each sampling period to a small valuerelative to the period therebetween.

8. The apparatus of claim 7, wherein the duration of each of saidsampling periods is approximately 1 millisecond and the periodtherebetween is approximately 250 milliseconds.

9. The apparatus of claim 1 wherein said time signal generator includesa minutes counter and an hours counter.

10. The apparatus of claim 9 wherein said time signal generator furtherincludes a time adjust circuit for individually adjusting said minutescounter and said hours counter.

11. The apparatus of claim 1 wherein said level converting meansincludes means coupled directly to said source of clock pulses forconverting said relatively low voltage pulses to relatively high voltagedisplay actuation signals for indicating that said electronictimekeeping system is operational.

'12. The apparatus of claim 1 wherein said level con- I verting meanscomprises a plurality of level converters 13. The apparatus of claim 12further including an additional level converter coupled to said timesignal generator for providing a relatively high voltage referencesignal, and a plurality of transfer gates each coupled to a differentone of said level converters and said additional level converter forgenerating said display actuation signals in response to said relativelyhigh voltage control signals.

14. The apparatus of claim 13 further including means coupled to saidadditional level converters for shaping said high voltage referencesignal.

15. The apparatus of claim l3 wherein said additional level converterprovides a periodic high voltage reference signal having a frequencysubstantially higher than the frequency of said control signals.

16. In an electronic watch having a means for providing a relatively lowD.C. supply voltage, a source of reference clock pulses, a timekeepingunit for providing a plurality of time indicating signals in response tosaid clock pulses, said clock pulse source and said timekeeping unitbeing powered by said low voltage supply means, a display operable at arelatively high voltage for providing a visible time indication, andmeans for converting said relatively low voltage to said relatively highvoltage the improvement comprising a plurality of level converting meanscoupled-to said timekeeping unit and said voltage converting means forconverting each of said time indicating signals to a level having amagnitude of the order of said relatively high D.C. voltage, saidimprovement enabling said watch to operate with low power consumption.

'17. The apparatus of claim 16 wherein each of said level convertingmeans comprises a level converter for converting the associated timeindicating signal to a relatively high voltage control signal, andtransfer means for generating a display actuation signal in response tosaid relatively high voltage control signal.'

18. The apparatus of claim 17 further including an 7 additional levelconverter coupled to said source for providing a relatively high voltagesupply signal for said transfer means.

19. The apparatus of claim 17 wherein said level con- UNITED sTATEsPATENT OFFICE CERTIFICATE OF CORRECTION Patent NO. 3!8l5!354 Dated June1974 Richard L. Sirocka et al It is certified that error appears in theabove-identified patent and that said Letters Patent are herebycorrected as shown below:

On the title page correct the designation of the first inventor bycancelling "Strocka" and inserting "Sirocka.

Signed and Scaled this I Twenty-sixth Day of October 1976 [SEAL] A nest:

RUTH C. MASON Arresting Officer C. MARSHALL DANN Commissioner oflarentsand Trademarks UNITED sTATEs PATENT OFFICE CERTIFICATE OF CORRECTIONPatent NQ. 15,354 Dated June 11, 1974 Inventor) Richard L. Sirocka et alIt is certified that error appears in the above-identified patent andthat said Letters Patent are hereby corrected as shown below:

On the title page correct the designation of the first inventor bycancelling "Strocka" and inserting "Sirocka.

Signed and Sealed this Twenty-sixth Day'of October 1976 [SEAL] Arrest:

RUTH C. MA'SON C. MARSHALL DANN AHPSII'IS ff Commissioner nfPatenls andTrademarks

1. An electronic timekeeping system characterized by low powerconsumption, said system comprising a source of relatively low D.C.voltage; means for converting the output from said source of relativelylow voltage to a relatively high D.C. voltage; a source of relativelylow voltage clock pulses; a time signal generator coupled to said sourceof clock pulses for providing a plurality of time signals having amagnitude of the order of said low voltage, said clock pulse source andsaid time signal generator being coupled to and powered by said sourceof relatively low D.C. voltage; and level converting means coupled tosaid time signal generator and said voltage converting means forconverting individual ones of said plurality of low voltage time signalsto display actuation signals having a magnitude of the order of saidrelatively high D.C. voltage.
 2. The apparatus of claim 1 furtherincluding display means coupled to said level converter means andoperable by said relatively high voltage display actuation signals forgenerating visible time indicia in response to said time signals.
 3. Theapparatus of claim 2 wherein said display means comprising a liquidcrystal display having a plurality of seven-segment digit characters. 4.The apparatus of claim 1 wherein said voltage converting means includesmeans for maintaining the magnitude of said relatively high voltageabove a predetermined threshold value.
 5. The apparatus of claim 4,wherein said maintaining means includes a threshold detector forgenerating an enabling signal when the magnitude of said high voltagedecreases to said predetermined threshold value.
 6. The apparatus ofclaim 5, wherein said maintaining means further includes sample meansfor periodically sampling the output of said threshold detector, andsense and enable means for generating a control signal adapted toactuate said voltage converting means in response to the generation ofsaid enabling signal.
 7. The apparatus of claim 6, wherein said samplemeans includes means for limiting the duration of each sampling periodto a small value relative to the period therebetween.
 8. The apparatusof claim 7, wherein the duration of each of said sampling periods isapproximately 1 millisecond and the period therebetween is approximately250 milliseconds.
 9. The apparatus of claim 1 wherein said time signalgenerator includes a minutes counter and an hours counter.
 10. Theapparatus of claim 9 wherein said time signal generator further includesa time adjust circuit for individually adjusting said minutes counterand said hours counter.
 11. The apparatus of claim 1 wherein said levelconverting means includes means coupled directly to said source of clockpulses for converting said relatively low voltage pulses to relativelyhigh voltage display actuation signals for indicating that saidelectronic timekeeping system is operational.
 12. The apparatus of claim1 wherein said level converting means comprises a plurality of levelconverters each coupled to a separate one of said plurality of timesignals for converting said relatively low voltage time signals to aplurality of relatively high voltage control signals, each of said levelconverters comprising bi-stable circuitry switchable between oppositestates, said bi-stable circuitry being complementarily configured torequire significant amounts of current only during switching.
 13. Theapparatus of claim 12 further including an additional level convertercoupled to said time signal generator for providing a relatively highvoltage reference signal, and a plurality of transfer gates each coupledto a different one of said level converters and said additional levelconverter for generating said display actuation signals in response tosaid relatively high voltage control signals.
 14. The apparatus of claim13 further including means coupled to said additional level convertersfor shaping said high voltage reference signal.
 15. The apparatus ofclaim 13 wherein said additional level converter provides a periodichigh voltage reference signal having a frequency substantially higherthan the frequency of said control signals.
 16. In an electronic watchhaving a means for providing a relatively low D.C. supply voltage, asource of reference clock pulses, a timekeeping unit for providing aplurality of time indicating signals in response to said clock pulses,said clock pulse source and said time-keeping unit being powered by saidlow voltage supply means, a display operable at a relatively highvoltage for providing a visible time indication, and means forconverting said relatively low voltage to said relatively high voltagethe improvement comprising a plurality of level converting means coupledto said timekeeping unit and said voltage converting means forconverting each of said time indicating signals to a level having amagnitude of the order of said relatively high D.C. voltage, saidimprovement enabling said watch to operate with low power consumption.17. The apparatus of claim 16 wherein each of said level convertingmeans comprises a level converter for converting the associated timeindicating signal to a relatively high voltage control signal, andtransfer means for generating a display actuation signal in response tosaid relatively high voltage control signal.
 18. The apparatus of claim17 further including an additional level converter coupled to saidsource for providing a relatively high voltage supply signal for saidtransfer means.
 19. The apparatus of claim 17 wherein said levelconverter comprises bi-stable circuitry switchable between oppositestates and complementarily configured to require significant amounts ofcurrent only during switching.